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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33790/D Rev 6.0, 02/2004
Advance Information Two-Channel Distributed System Interface (DSI) Physical Interface Device
The 33790 is a two-channel physical layer interface IC for the Distributed System Interface (DSI) bus. It is designed to meet automotive requirements. It can also be used in nonautomotive applications. It supports bidirectional communication between slave and master ICs. Some slave devices derive a regulated 5.0 V from the bus, which can be used to power sensors, thereby eliminating the need for additional circuitry and wiring. Features * Two Independent DSI Compatible Busses * Pinout Matched to MC68HC55 (SPI to DSI Logic) * Wave-Shaped Bus Output Voltage * Independent Thermal Shutdown and Current Limit * Return Signalling Current Detection * Internal Logic Input Pull-Ups and Pull-Downs * On-Board Charge Pump * 2.0 kV ESD Capability * Communications Rate Up to 150 kbps * Motorola now offers Pb-free packages with sufix code EG
33790
TWO-CHANNEL DISTRIBUTED SYSTEM INTERFACE (DSI) PHYSICAL INTERFACE DEVICE
Freescale Semiconductor, Inc...
EG (Pb free) SUFFIX DW SUFFIX CASE 751G
ORDERING INFORMATION
Device MC33790DW/R2 MC33790EG/R2 Temperature Range (TJ) -40C to 150C -40C to 150C Package 16 SOICW 16 SOICW
33790 Simplified Application Diagram
MC68HC55
DSI0F DSI0S DSI0R DSI1F DSI1S DSI1R CPCAP
33790
+5.0 V VDD GND DSI0O VSUP DSI1O GND DSIBUS1 DSIBUS0 +25 V 0.1 F
33791 BUS_IN
33793 BUS_OUT BUS_IN
DSI Slave Device BUS_IN
33927 BUS_OUT BUS_IN
This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2003
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VDD (+5.0 V)
CPCAP
VSUP (IDLE Level)
+
Internal Bias
Charge Pump
Bus Supply Voltage
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DSI0F DSI0S
WaveShaper Transmitter Driver
Bus Current Sense
DSI0O DSI Bus
DSI0R GND +
DSI1F DSI1S
WaveShaper Transmitter Driver
Bus Current Sense
DSI1O DSI Bus
DSI1R
Figure 1. 33790 Simplified Internal Block Diagram
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DSI0F DSI0S DSI0R DSI1F DSI1S DSI1R NC CPCAP
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD GND DSI0O VSUP DSI10 GND NC NC
PIN FUNCTION DESCRIPTION
Pin 1 Pin Name DSI0F DSI0S DSI0R DSI1F DSI1S DSI1R NC CPCAP NC NC GND DSI1O VSUP DSI0O GND VDD Description This logic input controls the frame output for DSI channel 0 in accordance with Table 1, page 8. This logic input controls the signalling output for DSI channel 0 in accordance with Table 1, page 8. This logic output provides the return data for DSI channel 0 in accordance with Table 1, page 8. This logic input controls the frame output for DSI channel 1 in accordance with Table 1, page 8. This logic input controls the signalling output for DSI channel 1 in accordance with Table 1, page 8. This logic output provides the return data for DSI channel 1 in accordance with Table 1, page 8. Unused. Used to store and filter charge pump output. Unused. Unused. Circuit and bus ground return. DSI bus 1 input/output. Idle level supply input. The voltage supplied to this pin sets the idle level on the DSI bus. DSI bus 0 input/output. Circuit and bus ground return. 5.0 V logic supply input.
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2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating Supply Voltage Continuous Load Dump - t < 300 ms Maximum Voltage on Input/Output Pins VSUP VSUP(t) VDD DSIxS, DSIxF (Note 1) DSIxO (Note 1) Storage Temperature Operating Junction Temperature TSTG TJ TSOLDER VDD DSIxR VSUP Thermal Resistance Junction to Ambient Thermal Shutdown ESD Voltage (All Pins) Human Body Model (Note 2) Machine Model (Note 3) VESD1 VESD2 2000 200 RJA TSD -0.5 to 25 40 -0.3 to 5.5 -0.3 to VDD +0.3 -0.3 to VSUP +0.3 -55 to 150 -40 to 150 230 0 to 10 -2.5 to 5.0 500 45 155 to 190 C/W C V C C C mA V Symbol Value Unit V
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Lead Temperature (IR Reflow Soldering for >60 s @ >183C), 10 s @ >215C Continuous Current per Pin
Notes 1. R = 0 . 2. ESD1 performed in accordance with the Human Body Model (CZAP =100pF, RZAP =1500 ). 3. ESD2 performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 ).
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V VDD 5.25 V, 8.0 V VSUP 25.0 V, -40C TJ 150C unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SUPPLY
ISUP Supply Current /Channel (Not Including IOUT) DSIx0 = Idle Voltage, -100 mA IOUT 0 mA DSIx0 = Output High Voltage, IOUT = 12 mA IDD Supply Current /Channel ISUPI ISUPH IDD - - - 1.35 5.0 0.5 3.25 9.00 1.0 mA mA
BUS TRANSMITTER
VSUP to DSIxO ON Resistance (During Idle) RDS(on) - DSIVOH 4.175 DSIVOL 1.325 ICLH ICLL DSIIB -200 - 50 -100 110 1.5 - - 1.675 -200 220 mA mA A 4.5 4.825 V - 10 V IOUT = -100 mA Output High Voltage DSIx0 (-15 mA IOUT 1.0 mA) Output Low Voltage DSIx0 (-15 mA IOUT 1.0 mA) Output High-Side Current Limit (Note 4) Output Low-Side Current Limit (Note 4) Input Leakage DSIxO When DSIxF Is High and DSIxS Is Low (0 V DSIxO Min (VSUP = 16.5 V))
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BUS RECEIVER
Return Current Threshold IRH -5.0 -6.0 -7.0 mA
MICROCONTROLLER INTERFACE
Logic Input Thresholds DSIxS, DSIxF Output High Voltage DSIxR Pin = -0.5 mA Output Low Voltage DSIxR Pin = 1.0 mA Internal Pull-Up for DSIxF Internal Pull-Down for DSIxS Notes 4. After 10 s settling time (assured by design). IIL IIH VOL 0.0 -100 10 - - - 0.2 * VDD -10 100 A A VIN(TH) VOH 0.8 * VDD - VDD V 1.10 - 2.20 V V
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DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V VDD 5.25 V, 8.0 V VSUP 25.0 V, -40C TJ 150C unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
MICROCONTROLLER INTERFACE
Microcontroller Signal Cycle Time Microcontroller Signal Low Time Microcontroller Signal High Time Microcontroller Signal Duty Cycle for Logic Zero Microcontroller Signal Duty Cycle for Logic One Microcontroller Signal Slew Time (Note 5) t cyc t cycL t cycH DCLo DCHi t slew t DLY1 t DLY2 t RISE t FALL 6.6 2.0 2.0 30 60.0 - t cyc -0.1 1.0 0 0 - - - 33 66.7 - t cyc - - - 1000 667 667 36 72.0 500 t cyc +0.1 - 100 100 s s s % % ns s s ns ns
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Frame Start to Signal Delay Time Signal End to Frame End Delay Time Rise Time (Note 5) Fall Time (Note 5)
BUS TRANSMITTER
Idle to Frame and Frame to Idle Slew Rate C 5.0 nF Signal High to Low and Signal Low to High Slew Rate C 5.0 nF Data Valid (VSUPx = 25 V, CL 5.0 nF) DSIxF, VIN(TH) to DSIxO = 5.3 V DSIxS, VIN(TH) to DSIxO = 2.6 V DSIxS, VIN(TH) to DSIxO = 3.4 V DSIxF, VIN(TH) to DSIxO = 7.0 V t DVLD1 t DVLD2 tDVLD3 tDVLD4 2.44 0.25 0.25 0.25 - - - - 6.56 1.3 1.3 1.3 t slew (SIGNAL) 3.0 4.5 8.0 s t slew (FRAME) 3.0 6.0 10.0 V/s V/s
BUS RECEIVER
Receiver Delay Time I = 9.0 mA to DSIxR = 0.8 * VDD I = -1.0 mA to DSIxR = 0.2 * VDD t DRH t DRL - - 400 400 750 750 ns
Notes 5. Slew times and rise and fall times between 10% and 90% of output high and low levels.
33790 6
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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tcyc tcycH 5.0 V
tcyc tDLY2
DSIxS
VIN(TH) 0V tcycL tDLY1 5.0 V tRISE tFALL tRISE
DSIxF
VIN(TH)
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0V 25 V 7.0 V tDVLD1 tDVLD3 tDVLD2 tslew(FRAME) tslew(SIGNAL)
tDVLD4
DSIxO 5.0 V
4.5 V
1.5 V
IOUT
6.0 mA 0 mA tDRH 5.0 V tDRL
DSIxR
0V
Figure 2. Timing Characteristics
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33790 is designed to provide the interface between logic and the DSI bus. It accepts signals with a typical 0 V to 5.0 V logic level to control the state of the bus output (Idle Level, Logic High Level, Logic Low Level, and High Impedance). It detects the current drawn from the bus output during signaling and outputs a 0 V to 5.0 V logic level corresponding to the bus current being above (Logic [1] out) the bus return logic [1] current or below (Logic [0] out). The 33790 contains current limiting of the bus outputs as required by the DSI Bus specification and thermal shutdown to protect itself from damage. Two independent DSI bus outputs are provided by the IC.
FUNCTIONAL DESCRIPTION Bus Driver and Receiver
Internal thermal shutdown circuitry and current limit individually protect the DSIxO outputs from shorts to battery and ground. Typically, the thermal shutdown occurs between 160C and 170C. If the junction temperature rises above this temperature, the output drivers for DSIxO are disabled by the thermal shutdown circuitry. The output drivers remain off until the junction temperature decreases below approximately 155C, at which time the thermal shutdown circuitry turns off and the outputs are re-enabled. Each DSIxO output has a unique thermal sense and shutdown circuit, so a short on one channel does not affect the other channel.
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The Wave-Shaper converts the 0 V to 5.0 V logic inputs from DSIxF (frame) and DSIxS (signal) to a wave-shaped signal on the DSIxO output, as shown in the timing diagrams in Figure 2, page 7, and the truth table in Table 1. The Bus Current Sense detects the current being drawn by the device(s) on the bus during signalling (DSIxF=0). If the current is above a set level, DSIxR will be high; otherwise, it is low. Table 1. DSI Bus Truth Table
DSIxF 0 0 1 1 X DSIxS 0 1 0 1 X TLIM 0 0 0 0 1 DSIR Return Data Return Data 0 0 1 DSIxO Low (1.5 V) High (4.5 V) High Impedance IdleVSUP -0.5 V High Impedance
Charge Pump
The charge pump uses on-board capacitors to step the input voltage up to the voltage needed to drive the on-board transmitter FETs. A filter/storage capacitor is connected to CPCAP to hold the stepped-up voltage.
The current for the idle state is from the supply connected to VSUP and this supply should not be current limited below 250 mA per channel. During idle state, the voltage on the DSI bus will be very close to the VSUP voltage.
Input Pull-Ups and Pull-Downs
Internal current pull-ups are used on the DSIxF pins and pulldowns on the DSIxS pins. If these pins are left unconnected, their associated DSI bus will go to the unused (high impedance) state.
APPLICATIONS
The 33790 is intended for use in a DSI system. This device supplies the interface between standard logic levels and the voltage and current required for the DSI bus. Two independent DSI busses are supported by this part. The 33790 does not form the timing for the DSI bus. This is done by logic either embedded in a microcontroller or by the MC68HC55, which uses SPI commands and forms DSI protocol for communications over the DSI bus. The pins from the MC68HC55 are made to line up with the pins connecting to the 33790. This includes all the DSIxF, DSIxS, and DSIxR pins. A capacitor attached to CPCAP serves as a charge reservoir for the gate drive charge pump. This circuit creates a voltage that is higher than the source of the N-channel output transistor. This allows turning on of the transistor enough to prevent any significant voltage drop across it. The rest of charge pump electronics are completely self-contained on the IC.
33790 8
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PACKAGE DIMENSIONS
EG (Pb free)SUFFIX DW SUFFIX 16-LEAD SOIC WIDE BODY PLASTIC PACKAGE CASE 751G-04 ISSUE D
0.25
PIN'S NUMBER 1 8X M
B A
10.55 10.05
16
2.65 2.35
0.25 0.10
16X
0.49 0.35 0.25
6
M
TAB
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62mm.
PIN 1 INDEX
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A
4 A
10.45 10.15
14X
1.27
8
9
7.6 7.4 5
T B
16X
SEATING PLANE
0.1 T
0.75 0.25
X45
0.32 0.23
1.0 0.4 SECTION A-A
7 0
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NOTES
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33790 10
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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NOTES
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2003 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors
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